Abstract—In this paper we present simulation of optimization of branch prediction in parallel register sharing architecture to show high degree of ILP. The main idea behind this concept is to use a step beyond the prediction of common branch and permitting the architecture to have the information about the CFG (Control Flow Graph) components of the program to have better branch decision for ILP. The navigation bandwidth of prediction mechanism depends upon the degree of ILP. It can be increased by increasing control flow prediction in procedural languages at compile time. By this the size of initiation is increased that allows the overlapped execution of multiple independent flow of control. The multiple branch instruction can also be allowed. These are intermediate steps to be taken in order to increase the size of dynamic window to achieve a high degree of ILP exploitation.
Index Terms—Basic Block, CFG, CFP, ILP.
Rajendra Kumar is with Computer Science and engineering Department, Vidya College of Engineering, Meerut (Uttar Pradesh), India (phone: +91- 9412002322, e-mail: rajendra04@gmail.com, website: http://www.rkronline.in).
P. K. Singh is with the Computer Science and engineering Department, MMM Engineering College, Gorakhpur (Uttar Pradesh), India (e-mail: topksingh@gmail.com).
Cite: Rajendra Kumar and P. K. Singh, "Simulation of Branch Prediction Optimization in Parallel Register Sharing Architecture," International Journal of Modeling and Optimization vol. 2, no. 5, pp. 575-578, 2012.
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