Abstract—In present work a new XOR gate using three transistors has been proposed. Design shows adequate output logic levels with noise margin of 2V with 3.3V input signals. XNOR logic, obtained with addition of inverter shows improved noise margin of 3.2V. A new design for single bit full adder has been implemented using proposed XOR/XNOR gates and transmission gate multiplexer. Full adder designed with 14 transistors shows power dissipation of 655.6149μW and maximum output delay 0.11055ns. Proposed adder circuit shows adequate noise margin of 3.2 V for Sum (Sum output) and 2.2V for Cout (Carry output) with supply voltage of 3.3V. Circuit works well with reduced supply voltage and simulations have been carried out up to 1.8V supply voltage. Simulations are performed by using SPICE based on TSMC 0.35μm CMOS technology. Power consumption of proposed full adders has been compared with earlier reported circuits and proposed circuit’s shows better performance in terms of power consumptions and transistor count.
Index Terms—CMOS, exclusive-OR (XOR), exclusive-NOR (XNOR), full adder design, low power and transmission gate.
Dr. Sandeep K. Arya is with the Department of Electronics & Communication Engineering, Guru Jambheshwar University of Science & Technology, Hisar, India (e-mail: email@example.com).
Dr. Sujata Pandey is with the Department of Electronics & Communication Engineering, Amity University, Noida, India (e-mail: firstname.lastname@example.org).
Cite: Manoj Kumar, Sandeep K. Arya, and Sujata Pandey, "A New Low Power Single Bit Full Adder Design with 14 Transistors using Novel 3 Transistors XOR Gate," International Journal of Modeling and Optimization vol. 2, no. 4, pp. 544-548, 2012.