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General Information
Editor-in-chief
Prof. Adrian Olaru
University Politehnica of Bucharest, Romania
I'm happy to take on the position of editor in chief of IJMO. It's a journal that shows promise of becoming a recognized journal in the area of modelling and optimization. I'll work together with the editors to help it progress.
IJMO 2012 Vol.2(3): 263-268 ISSN: 2010-3697
DOI: 10.7763/IJMO.2012.V2.124

A Real Measurement Power Tool for Intellectual Property on FPGA

N. Chalbi, M. Boubaker, and M. H. Bedoui

Abstract—The FPGA (Field Programmable Gate Array) power consumption has become a very critical problem for new technologies. Also, in order to develop embedded systems it is necessary to controll this parameter at a high level of the conception design. For these reasons, we present in this paper an RTL (Register Transfer Level) IPs (Intellectual Property) power models. The characterization phase of the dynamic power variation was carried out by using a real power measurement tool organized around of the XC2VP4 (Virtex-II Pro) device. The RTL models were elaborated according to the clock frequency and input activity rate. The accuracy of the adopted methodology has been justified by comparing our results with the UAM (University Autonoma Madrid) and the Xilinx Xpower tools.

Index Terms—FPGA power consumption, real power measurement tool, characterization, accuracy.

N. Chalbi is now with the Biophysics laboratory, TIM Project; Medical Faculty of Monastir, Monastir, TUNISIA (e-mail: naj_chalbi@yahoo.fr).
M. Boubaker is now with the Biophysics laboratory, TIM Project; Medical Faculty of Monastir, Monastir, TUNISIA (e-mail: boubaker_mohamed@yahoo.fr).
M. H. Bedoui is now with the Biophysics laboratory, TIM Project; Medical Faculty of Monastir, Monastir, TUNISIA (e-mail: medhedi.bedoui@fmm.rnu.tn).

[PDF]

Cite: N. Chalbi, M. Boubaker, and M. H. Bedoui, "A Real Measurement Power Tool for Intellectual Property on FPGA," International Journal of Modeling and Optimization vol. 2, no. 3, pp. 263-268, 2012.

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