Abstract—The advancement in silicon material processes technology in the manufacture of 45nm MOSFET has extended Moore’s Law for some more years. Low power CMOS circuit design has become a challenge due to variations in design parameters caused as a result of short channel effects at deep submicron levels for technology nodes below 1μm. In this paper, we have analyzed the design aspects for short channel devices by method of transistor modeling and further simulations have been carried out using Virtuoso cadence Simulator. The technology nodes considered here are 180nm and 45nm technology since fabrication of 180nm uses conventional process technology and 45nm uses new innovations in process technology. The aim of this paper is to bring out parameter variability issues related to different process technologies and find solutions for power optimization at design level for CMOS circuits.
Index Terms—Short channel effects, CMOS, technology node; Threshold variation, low power, scaling
Kiran Agarwal Gupta is with Dayananda Sagar College of Engineering in the dept. of E&C as Associate Professor.Bangalore-560078, India.(e-mail:jpkiran9@gmail.com, g.kiran@ieee.org).
Dinesh Anvekar is with Honeywell Technology Solution Labs as Six Sigma Specialist for Research and Innovations Bangalore-560078, India (e-mail: Dinesh.Anvekar@honeywell.com).
V. Venkateswarlu is with United Technologies Limited working as professor and Principal of VTU Extension Centre.Bangalore-560022, India (e-mail:vwarlu@utltraining.com)
[PDF]
Cite:Kiran Agarwal Gupta, Dinesh K. Anvekar, and Venkateswarlu V., "Modeling of Short Channel MOSFET Devices and Analysis of Design Aspects for Power Optimisation," International Journal of Modeling and Optimization vol. 3, no. 3, pp. 266-271, 2013.
