Abstract—Packet-switched networks for communications within large multi core systems on-chip are made for enhanced performance, scalability, modularity, and design productivity more than previous communication architectures such as busses and dedicated signal wires. Multiprocessor architectures and platforms have been introduced to extend the applicability of Moore’s law. They depend on concurrency and synchronization in both software and hardware to enhance the design productivity and system performance. These platforms will also have to incorporate highly scalable, reusable, predictable, cost- and energy efficient architectures. With the rapidly approaching billion transistors era, some of the main problems in deep sub-micron technologies which are characterized by gate lengths in the range of 60-90 nm, will arise from non-scalable wire delays, errors in signal integrity and unsynchronized communications. These problems may be overcome by the use of Network on Chip architecture. The proposed paper is a survey of various research papers and contributions in NOC area.
Index Terms—Packet-switched networks, multi-core, on chip architectures, network on chip.
R. Mutha was with the JIET Group of Institutions, Jodhpur, Rajasthan, India. (e-mail: rakhimutha@gmail.com).
Cite: Rakhi Mutha, "Packet Switched Networks for Communications within Large Multi-Core Systems on Chip," International Journal of Modeling and Optimization vol. 2, no. 4, pp. 422-426, 2012.
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