Segmented Buffer for NOC Router - Volume 5 Number 1 (Feb. 2015) - ijmo
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General Information
Editor-in-chief
Prof. Adrian Olaru
University Politehnica of Bucharest, Romania
I'm happy to take on the position of editor in chief of IJMO. It's a journal that shows promise of becoming a recognized journal in the area of modelling and optimization. I'll work together with the editors to help it progress.
IJMO 2015 Vol.5(1): 32-35 ISSN: 2010-3697
DOI: 10.7763/IJMO.2015.V5.431

Segmented Buffer for NOC Router

Biman Debbarma and S. N. Pradhan
Abstract—As the number of transistors in a single chip is increasing day by day, SoC is a very popular choice among the developers as it gives more speed and functionality. The IPs in the SoCs can be from different vendors and may be used for a third party for manufacturing a chip. For effective communication among the IPs or more commonly Cores, an in built network structure called Network on Chip (NOC) has been developed over the years and different versions of NOCs are available in the present day. This paper proposes a segmented buffer structure for NOC router for effective utilization of the NOC buffers.

Index Terms—Router, ViCHAR, segmented buffer, segmented control logic, power gating.

Biman Debbarma and S. N. Pradhan are with the National Institute of Technology Agartala, India (e-mail: bimandebbarma75@gmail.com).

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Cite: Biman Debbarma and S. N. Pradhan, "Segmented Buffer for NOC Router," International Journal of Modeling and Optimization vol. 5, no. 1, pp. 32-35, 2015.

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