• May 15, 2019 News!Vol.7, No.5- Vol.8, No.4 has been indexed by EI (Inspec).   [Click]
  • Aug 01, 2018 News! [CFP] 2020 the annual meeting of IJMO Editorial Board, ECDMO 2020, will be held in Athens, Greece, February 15-17, 2020.   [Click]
  • Sep 30, 2019 News!Vol 9, No 6 has been published with online version. 12 original aritcles from 6 countries are published in this issue.    [Click]
General Information
    • ISSN: 2010-3697  (Online)
    • Abbreviated Title: Int. J. Model. Optim.
    • Frequency: Bimonthly
    • DOI: 10.7763/IJMO
    • Editor-in-Chief: Prof. Adrian Olaru
    • Executive Editor: Ms.Yoyo Y. Zhou
    • Abstracting/ Indexing: ProQuest, Crossref, Electronic Journals Library, Google Scholar, EI (INSPEC, IET), EBSCO, etc.
    • E-mail ijmo@iacsitp.com
Prof. Adrian Olaru
University Politehnica of Bucharest, Romania
I'm happy to take on the position of editor in chief of IJMO. It's a journal that shows promise of becoming a recognized journal in the area of modelling and optimization. I'll work together with the editors to help it progress.
IJMO 2014Vol.4(1): 74-80 ISSN: 2010-3697
DOI: 10.7763/IJMO.2014.V4.350

Circuit Partitioning for Behavioral Full Chip Simulation Modeling of Analog and Mixed Signal Circuits

Samantha Alt, Malgorzata Marek-Sadowska, and Li. C. Wang
Abstract—This paper presents a new method for automatically creating transient voltage behavioral models of analog and mixed signal circuits based on functionally independent partitions. The models are obtained using Support Vector Machines (SVM), a data dependent black box modeling technique. Larger circuits are partitioned based on their structure and intermediate behavioral models are built for high sensitivity nets. The models are implemented in System Verilog for use in full chip system validation. We demonstrate the soundness of this approach by modeling large and highly non-linear circuits such as Sigma-Delta Analog-to- Digital (ADC) and jitter of a Phase Lock Loop. Experimental results show 95% accuracy behavior predictions and three orders of magnitude speedup over SPICE simulation time.

Index Terms—Circuit partition, support vector machines, channel connected component graph, behavioral models.

The authors are with the University of California, Santa Barbara, CA 93107 USA (e-mail: {salt,mms,licwang}@ ece.ucsb.edu).


Cite: Samantha Alt, Malgorzata Marek-Sadowska, and Li. C. Wang, "Circuit Partitioning for Behavioral Full Chip Simulation Modeling of Analog and Mixed Signal Circuits," International Journal of Modeling and Optimization vol. 4, no. 1, pp. 74-80, 2014.

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