Abstract—This paper presents a new method for
automatically creating transient voltage behavioral models of
analog and mixed signal circuits based on functionally
independent partitions. The models are obtained using
Support Vector Machines (SVM), a data dependent black box
modeling technique. Larger circuits are partitioned based on
their structure and intermediate behavioral models are built
for high sensitivity nets. The models are implemented in
System Verilog for use in full chip system validation. We
demonstrate the soundness of this approach by modeling large
and highly non-linear circuits such as Sigma-Delta Analog-to-
Digital (ADC) and jitter of a Phase Lock Loop. Experimental
results show 95% accuracy behavior predictions and three
orders of magnitude speedup over SPICE simulation time.
Index Terms—Circuit partition, support vector machines,
channel connected component graph, behavioral models.
The authors are with the University of California, Santa Barbara, CA
93107 USA (e-mail: {salt,mms,licwang}@ ece.ucsb.edu).
[PDF]
Cite: Samantha Alt, Malgorzata Marek-Sadowska, and Li. C. Wang, "Circuit Partitioning for Behavioral Full Chip Simulation
Modeling of Analog and Mixed Signal Circuits," International Journal of Modeling and Optimization vol. 4, no. 1, pp. 74-80, 2014.
