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General Information
Prof. Adrian Olaru
University Politehnica of Bucharest, Romania
I'm happy to take on the position of editor in chief of IJMO. It's a journal that shows promise of becoming a recognized journal in the area of modelling and optimization. I'll work together with the editors to help it progress.
IJMO 2013 Vol.3(1): 92-94 ISSN: 2010-3697
DOI: 10.7763/IJMO.2013.V3.242

High Speed FPGA Implementation of FIR Filter for DSP Applications

Rakhi Thakur and Kavita Khare

Abstract—Signal processing ranks among the most demanding applications of digital design concepts. It is a mature technology domain wherein the demands for enhanced performance and reduced resource utilization have risen exponentially over the years. Field Programmable Gate Array (FPGA) design technology has becoming the preferred platform for evaluating and implementing signal processing algorithms. The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an application specific integrated circuit (ASIC) for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. This paper describes an approach to the implementation of digital filter based on field programmable gate arrays (FPGAs) which is flexible and provides performance comparable or superior to traditional approaches, lowpower, area-efficient re-configurable digital signal processing architecture that is tailored for the realization of arbitrary response Finite impulse response (FIR) filters.

Index Terms—FIR Filter, FPGA, DSP chips.

Rakhi Thakur is with Kalaniketan Polytechnic college Jabalpur Madhya Pradesh India (rakhi082003@yahoo.co.in)
Kavita Khare is with Maulana Azad National institute of technology Bhopal India (kavitakhare1@yahoo.co.in )


Cite: Rakhi Thakur and Kavita Khare, "High Speed FPGA Implementation of FIR Filter for DSP Applications," International Journal of Modeling and Optimization vol. 3, no. 1, pp. 92-94, 2013.

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