• May 15, 2019 News!Vol.7, No.5- Vol.8, No.4 has been indexed by EI (Inspec).   [Click]
  • Aug 01, 2018 News! [CFP] 2020 the annual meeting of IJMO Editorial Board, ECDMO 2020, will be held in Athens, Greece, February 15-17, 2020.   [Click]
  • Sep 30, 2019 News!Vol 9, No 6 has been published with online version. 12 original aritcles from 6 countries are published in this issue.    [Click]
General Information
    • ISSN: 2010-3697  (Online)
    • Abbreviated Title: Int. J. Model. Optim.
    • Frequency: Bimonthly
    • DOI: 10.7763/IJMO
    • Editor-in-Chief: Prof. Adrian Olaru
    • Executive Editor: Ms.Yoyo Y. Zhou
    • Abstracting/ Indexing: ProQuest, Crossref, Electronic Journals Library, Google Scholar, EI (INSPEC, IET), EBSCO, etc.
    • E-mail ijmo@iacsitp.com
Prof. Adrian Olaru
University Politehnica of Bucharest, Romania
I'm happy to take on the position of editor in chief of IJMO. It's a journal that shows promise of becoming a recognized journal in the area of modelling and optimization. I'll work together with the editors to help it progress.
IJMO 2019 Vol.9(2): 87-91 ISSN: 2010-3697
DOI: 10.7763/IJMO.2019.V9.690

Building Robust Designs for Best Process Scaling

Rafi M. Saied and Zi Wen
Abstract—The demand for Multi Giga Hertz high performance microprocessors continues to increase along with the need to support many modes of operations under multiple conditions. The demand from mission critical servers and data farms require that these are robust, reliable and perform at peak performance under all conditions. The devices must be able to work at high speeds to meet the performance demands, quickly and reliably which causes increasing challenges in hardware designs to ensure the machine is both robust and reliable in diverse conditions. There are many aspects involved in performance verification of design such as process technology, voltage, temperature, library design, routing, and the system conditions. In order to model all of this correctly, design has to be verified under multiple PVT (Process, voltage and Temperature) conditions. We need to account for the variation that comes with different voltages and temperature conditions [1], for example how the device behaves at 0.55V vs. 1.1v. In this paper we show how some of these challenges can be addressed through Best Design techniques, Mode of work, and methodology changes to get the design that is robust across different PVTs and reduce process variation impact.

Index Terms—Process scaling, PVT modes, modelling, scalability, efficiency, time to market

Rafi M Saied is a Senior Staff Engineer at Intel Corp. in Folsom, USA (e-mail: rafi.saied@intel.com)


Cite: Rafi M. Saied and Zi Wen, "Building Robust Designs for Best Process Scaling," International Journal of Modeling and Optimization vol. 9, no. 2, pp. 页, 2019.

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