Abstract—Adaptive systems based on Field- Programmable Gate Array (FPGA) architectures can benefit from the high degree of flexibility offered by Dynamic Partial Reconfiguration (DPR). In DPR, hardware modules composing an application can be allocated on demand or depending on a dynamically changing system. However, founders DPR tools are limited in functionality because it does not support an automatic place- ment, and require a manual inputs from the design. Manual placement not allows an efficient placement. The placement step represents a critical step in DPR flow on FPGA. It is highly impact routability, timing and density, hence performance of the system. In this paper, we present a novel placement algorithm to address these constraints by offering minimal fragmentation that minimizes resource utilization and reduces the total wirelength. The selection of the Partial Reconfigurable Region (PRR) is based on the shapes, location and communication with others. The proposed approach has been experimentally evaluated with a case study. Experimental results show the effectiveness of the proposed algorithm in the terms of exploration area and communication cost.
Index Terms—Placement, FPGA, dynamic partial reconfigura- tion, wirelength
M. Naouss and M. Hannachi are with the Department of research, Altran Technologies, Toulouse, France (e-mail: mohammad.naouss@altran.com, marwa.hannachi@altran.com).
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Cite: Mohammad Naouss and Marwa Hannachi, "Optimized Placement Approach on Reconfigurable FPGA," International Journal of Modeling and Optimization vol. 9, no. 2, pp. 82-86, 2019.
