—A new algorithm for parallel fault simulation of VLSI on multicore workstations with common memory is proposed. To speeding up the algorithm two-level parallelization is used. First, main schema of the algorithm is based on the concurrent many-threaded simulation of the groups of faults for each input vector. Second, each group of faults is simulated in bit-parallel way. The dynamic fault grouping is adopted. The results of computational experiments on ISCAS-89 benchmarks circuits are reported, which are obtained on the 12-core workstation.
—Fault simulation, multicore workstation, multithreaded programming, parallel calculation, VLSI circuit.
D. E. Ivanov is with Institute of Mathematics of National Academy of Sciences of Ukraine, Tereschenkivska st., 3, Ukraine (e-mail: email@example.com).
Cite: D. E. Ivanov, "Parallel Simulation Algorithm of VLSI for Multicore Workstations with Dynamic Faults Grouping," International Journal of Modeling and Optimization vol. 6, no. 3, pp. 166-170, 2016.