Parallel Simulation Algorithm of VLSI for Multicore Workstations with Dynamic Faults Grouping - Volume 6 Number 3 (Jun. 2016) - ijmo
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General Information
Editor-in-chief
Prof. Adrian Olaru
University Politehnica of Bucharest, Romania
I'm happy to take on the position of editor in chief of IJMO. It's a journal that shows promise of becoming a recognized journal in the area of modelling and optimization. I'll work together with the editors to help it progress.
IJMO 2016 Vol.6(3): 166-170 ISSN: 2010-3697
DOI: 10.7763/IJMO.2016.V6.522

Parallel Simulation Algorithm of VLSI for Multicore Workstations with Dynamic Faults Grouping

D. E. Ivanov
Abstract—A new algorithm for parallel fault simulation of VLSI on multicore workstations with common memory is proposed. To speeding up the algorithm two-level parallelization is used. First, main schema of the algorithm is based on the concurrent many-threaded simulation of the groups of faults for each input vector. Second, each group of faults is simulated in bit-parallel way. The dynamic fault grouping is adopted. The results of computational experiments on ISCAS-89 benchmarks circuits are reported, which are obtained on the 12-core workstation.

Index Terms—Fault simulation, multicore workstation, multithreaded programming, parallel calculation, VLSI circuit.

D. E. Ivanov is with Institute of Mathematics of National Academy of Sciences of Ukraine, Tereschenkivska st., 3, Ukraine (e-mail: dmitry.ivanov.iamm@gmail.com).

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Cite: D. E. Ivanov, "Parallel Simulation Algorithm of VLSI for Multicore Workstations with Dynamic Faults Grouping," International Journal of Modeling and Optimization vol. 6, no. 3, pp. 166-170, 2016.

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