Abstract—The bit-parallel multiplier over Galois filed arithmetic algorithm and the circuit architecture have been widely studied and implemented in cryptosystem. In this paper, we implement the proposed secure and low-power dual-rail adiabatic logic circuit into the bit-parallel cellular multiplier over GF(24). The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155 m2, and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS technology has achieved; while, the well-known conventional TDPL logic in our work using the same technology occupied 183×m2 of the chip size and 123pJ per cycle. The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the better security performance at high frequency range.
Index Terms—Bit-parallel multiplier, adiabatic, low-power, side channel attack, cryptography.
Cancio Monteiro is with the Graduate School of Engineering, Gifu University, 1-1 Yanagido, Gifu-shi, 501-1193, Japan (corresponding author, e-mail: canciotimor@gmail.com).
Yasuhiro Takahashi and Toshikazu Sekine are with Faculty of Engineering, Gifu University, 1-1 Yanagido, Gifu-shi, 501-1193, Japan (e-mail: {yasut,sekine}@gifu-u.ac.jp).
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Cite:Cancio Monteiro, Yasuhiro Takahashi, and Toshikazu Sekine, "Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic," International Journal of Modeling and Optimization vol. 3, no. 4, pp. 329-332, 2013.
