• Apr 24, 2017 News! Vol.6, No.4 has been indexed by EI (Inspec).   [Click]
  • Apr 24, 2017 News! Vol.6, No.3 has been indexed by EI (Inspec).   [Click]
  • May 24, 2017 News!Vol 7, No 2 has been published with online version 10 original aritcles from 6 countries are published in this issue   [Click]
General Information
    • ISSN: 2010-3697
    • Frequency: Bimonthly
    • DOI: 10.7763/IJMO
    • Editor-in-Chief: Prof. Adrian Olaru
    • Executive Editor: Ms.Yoyo Y. Zhou
    • Abstracting/ Indexing: Engineering & Technology Digital Library, ProQuest, Crossref, Electronic Journals Library, Google Scholar, EI (INSPEC, IET).
    • E-mail ijmo@iacsitp.com
Editor-in-chief
Prof. Adrian Olaru
University Politehnica of Bucharest, Romania
I'm happy to take on the position of editor in chief of IJMO. It's a journal that shows promise of becoming a recognized journal in the area of modelling and optimization. I'll work together with the editors to help it progress.
IJMO 2013 Vol.3(4): 329-332 ISSN: 2010-3697
DOI: 10.7763/IJMO.2013.V3.292

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Cancio Monteiro, Yasuhiro Takahashi, and Toshikazu Sekine
Abstract—The bit-parallel multiplier over Galois filed arithmetic algorithm and the circuit architecture have been widely studied and implemented in cryptosystem. In this paper, we implement the proposed secure and low-power dual-rail adiabatic logic circuit into the bit-parallel cellular multiplier over GF(24). The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155 m2, and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS technology has achieved; while, the well-known conventional TDPL logic in our work using the same technology occupied 183×m2 of the chip size and 123pJ per cycle. The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the better security performance at high frequency range.

Index Terms—Bit-parallel multiplier, adiabatic, low-power, side channel attack, cryptography.

Cancio Monteiro is with the Graduate School of Engineering, Gifu University, 1-1 Yanagido, Gifu-shi, 501-1193, Japan (corresponding author, e-mail: canciotimor@gmail.com).
Yasuhiro Takahashi and Toshikazu Sekine are with Faculty of Engineering, Gifu University, 1-1 Yanagido, Gifu-shi, 501-1193, Japan (e-mail: {yasut,sekine}@gifu-u.ac.jp).

[PDF]

Cite:Cancio Monteiro, Yasuhiro Takahashi, and Toshikazu Sekine, "Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic," International Journal of Modeling and Optimization vol. 3, no. 4, pp. 329-332, 2013.

Copyright © 2008-2015.International Journal of Modeling and Optimization. All rights reserved.
E-mail: ijmo@iacsitp.com