Abstract—High speed and low power Viterbi Decoder of rate ½ convolutional coding with a constraint length K = 3 is presented in this paper. After implementation of proposed Viterbi decoder in Virtex 7 Field Programmable Gate Array (FPGA) kit we come to know that it’s functioning on 413.121 MHz clock and in such a high speed it also maintain a low power of 11.34 mW in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one Integrated Circuit (IC) we can create a high speed and low power Viterbi decoder at the same time with some extra hardware area.
Index Terms—FPGA, viterbi decoder, low power, xilinx power estimator, high speed.
The authors are with Electrical Department, Digital System Design Lab, IIT Indore, MP, India (e-mail: phd11120203@iiti.ac.in, skvishvakarma@iiti.ac.in).
Cite: Pooran Singh and Santosh Kr. Vishvakarma, "FPGA Implementation of 413.121 MHz and 11.34 mW High Speed Low Power Viterbi Decoder," International Journal of Modeling and Optimization vol. 3, no. 1, pp. 15-19, 2013.
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