Abstract—This paper suggests a novel method to design and optimize synchronous sequential circuits. Genetic algorithm is applied as an evolutionary algorithm. There are two different approaches to design combinational part of sequential circuits. In the first approach, cell arrays are used for building input and output combinational logic circuit of each D Flip-Flops. In the second approach, for designing combinational parts, one rectangular array of logic gates is used to build next state of all DFFs and another one is used to build primary outputs. The obtained results indicate that our method can reduce the average number of generations and reduce the number of used gates. Also using the first approach can increase the evolution speed of the circuit in compare with the second approach.
Index Terms—Evolvable hardware, sequential logic circuit, combinational logic circuit, genetic algorithm.
P. Soleimani is with the Department of electronic engineering, Islamic Azad University, Central Tehran Branch. E-mail: parisa.soleimani@ gmail.com.
S. Mirzakuchaki is with the Department of electronic engineering, Iran University, of Science and Technology. E-mail: M_kuchaki@iust.ac.ir.
K. Mohammadi is with the Department of electronic engineering, Iran University, of Science and Technology. E-mail: mohammadi@iust.ac.ir.
M. Bagheri is with the Department of electronic engineering, Iran University, of Science and Technology. E-mail: m-bagheri@elec.iust.ac.ir.
Cite: P. Soleimani, S. Mirzakuchaki, K. Mohammadi, and M. Bagheri, "A Novel Evolutionary Design of Sequential Logic Circuits by Using Genetic Algorithm," International Journal of Modeling and Optimization vol. 1, no. 3, pp. 231-235, 2011.
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